Articles by subject: mcu & soc

Plot of a MicroBlaze system memory access latency and memory bandwidth versus the working set size.

MicroBlaze Benchmarks Part 2 – Memory Bandwidth & Latency

Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.

Read More »
Digilent ARTY7-35 development board with USB and Ethernet cables connected.

MicroBlaze Benchmarks Part 1 – CoreMark Performance

Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.

Read More »
Close up view of a MicroBlaze system within the Xilinx Vivado IP Integrator.

MicroBlaze Configuration for an RTOS Part 3 – Cache Configuration

This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.

Read More »
Close up of the MicroBlaze IP block within the Xilinx Vivado IP Integrator.

MicroBlaze Configuration for an RTOS Part 2 – Configuration Parameters

This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.

Read More »
Block diagrams of three types of on-chip RAM (OCRAM) topology.

Introduction to On-Chip RAM

On chip ram, often abbreviated OCRAM has been around since the earliest System on Chips(SoCs). In the beginning, on chip memory was relatively small and was primarily used by bootloaders and as simple scratch memory. On chip RAM has since evolved in terms of size, speed and features as SoCs became more complex to often

Read More »
Close-up view of Toradex Colibri iMX7 in evaluation board.

BASEplatform Bring-Up on the Toradex Colibri iMX7

This article will go over some aspects of the early bring-up experience using the BASEplatform™ on the Toradex Colibri iMX7 System on Module (SoM). It will also cover features and advantages of the Colibri SoM for embedded developers interested in using an RTOS or a bare-metal environment on the NXP® i.MX7 SoC. The BASEplatform is

Read More »
Histogram of interrupt latency distribution with pase fail sections for demonstration.

Estimating Worst Case Interrupt Latency at Runtime

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

Read More »
Close up view of the Digilent Zybo development board showing the Xilinx Zynq-7000 SoC.

Zynq-7000 Connectivity Using the uC/OS BSP

In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a

Read More »
Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

i.MX7D M4 Bare-Metal Bring-up and Benchmark

Following up on the last piece about the NXP i.MX 7, this article looks at the Cortex-M4 companion of the A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare metal

Read More »

Articles by subject: mcu & soc

Plot of a MicroBlaze system memory access latency and memory bandwidth versus the working set size.

MicroBlaze Benchmarks Part 2 – Memory Bandwidth & Latency

Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.

Read More »
Digilent ARTY7-35 development board with USB and Ethernet cables connected.

MicroBlaze Benchmarks Part 1 – CoreMark Performance

Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.

Read More »
Close up view of a MicroBlaze system within the Xilinx Vivado IP Integrator.

MicroBlaze Configuration for an RTOS Part 3 – Cache Configuration

This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.

Read More »
Close up of the MicroBlaze IP block within the Xilinx Vivado IP Integrator.

MicroBlaze Configuration for an RTOS Part 2 – Configuration Parameters

This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.

Read More »
Block diagrams of three types of on-chip RAM (OCRAM) topology.

Introduction to On-Chip RAM

On chip ram, often abbreviated OCRAM has been around since the earliest System on Chips(SoCs). In the beginning, on chip memory was relatively small and was primarily used by bootloaders and as simple scratch memory. On chip RAM has since evolved in terms of size, speed and features as SoCs became more complex to often

Read More »
Close-up view of Toradex Colibri iMX7 in evaluation board.

BASEplatform Bring-Up on the Toradex Colibri iMX7

This article will go over some aspects of the early bring-up experience using the BASEplatform™ on the Toradex Colibri iMX7 System on Module (SoM). It will also cover features and advantages of the Colibri SoM for embedded developers interested in using an RTOS or a bare-metal environment on the NXP® i.MX7 SoC. The BASEplatform is

Read More »
Histogram of interrupt latency distribution with pase fail sections for demonstration.

Estimating Worst Case Interrupt Latency at Runtime

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

Read More »
Close up view of the Digilent Zybo development board showing the Xilinx Zynq-7000 SoC.

Zynq-7000 Connectivity Using the uC/OS BSP

In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a

Read More »
Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

i.MX7D M4 Bare-Metal Bring-up and Benchmark

Following up on the last piece about the NXP i.MX 7, this article looks at the Cortex-M4 companion of the A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare metal

Read More »