benchmark

Comparing 4 Popular Embedded File Systems for NOR and NAND Flash

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In this article, we discuss 4 popular file systems for both NOR and NAND flash, commonly used in bare metal and RTOS-based embedded systems: LittleFS, Yaffs, FileX and TSFS. We provide a brief description of each file system and compare their performance, RAM consumption and other specific advantages and limitations. There are plenty of other … Read more

Setting up SPI NAND on Nordic’s nRF5340 (from A to Z)

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In this article, we explain how to connect, configure and access a serial NAND device connected through SPI to the Nordic Semiconductor’s nRF5340 MCU. In the process, we discuss serial flash fundamentals, write a fully functional SPI flash driver, and compare SPI and QSPI performances. For demonstration purposes, we use the nRF5340-DK development kit which … Read more

Zynq-7000 Bare-Metal Benchmarks

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Picture of a Zynq-7000 SoC.

In this article we’ll look at some well-known CPU benchmarks, namely CoreMARK, Dhrystone, Whetstone and Linpack. Following that, we’ll look at the memory bandwidth and latency of the external DDR memory, On-Chip RAM and block RAM (BRAM) in the FPGA. Finally, we’ll round up with numbers on interrupt latency.

Uncovering SD card Performances using Bare-Metal Benchmarks

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In this article, we present a detailed discussion of SD card performances along with benchmarks for consumer and industrial-grade cards. The results help quantify the large variations in performance between individual devices and their impact on real-world performance.

MicroBlaze Benchmarks Part 2 – Memory Bandwidth & Latency

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Plot of a MicroBlaze system memory access latency and memory bandwidth versus the working set size.

Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.

MicroBlaze Benchmarks Part 1 – CoreMark Performance

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Digilent ARTY7-35 development board with USB and Ethernet cables connected.

Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.

Estimating Worst Case Interrupt Latency at Runtime

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Histogram of interrupt latency distribution with pase fail sections for demonstration.

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

i.MX7D M4 Bare-Metal Bring-up and Benchmark

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Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

Following up on the last piece about the NXP i.MX 7, this article looks at the ARM Cortex-M4 companion of the Cortex-A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare … Read more

i.MX7D Sabre Bare-Metal Bring-up and Benchmark

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Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

One of our specialties at JBLopen is board bring-up, either for bare metal or various commercial and open source RTOSes. Despite the number of different platforms, CPU architectures and RTOSes out there, low level bring-up, BSP and driver development are rarely discussed in blogs and articles on the web. The same can be said about … Read more

Improving Interrupt Latency on the ARM Cortex-A9

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Interrupt latency distribution for a Cortex-A9 with cold cache.

Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9 which can help reduce interrupt latency. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 and 64 bits ARM processors such as the Cortex-A7. Newer cores have a simpler TLB, and most often than not an integrated L2 cache instead of the external L2 found on the A9. However, the Cortex-A9 is still a popular core, found on the Xilinx Zynq-7000 and NXP i.MX 6 SoCs to name a few.

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