Embedded Software Insight
This article discusses the performance limitations of the FAT file system with a focus on SD Card. After a brief refresher on FAT fundamentals, we show how FAT predictably achieves high access performances in the absence of fragmentation, but how fragmentation can build up until performances suddenly collapse. We conclude with a few important recommendations about the use of the FAT file system on embedded flash memory.
In this article we’ll look at some well-known CPU benchmarks, namely CoreMARK, Dhrystone, Whetstone and Linpack. Following that, we’ll look at the memory bandwidth and latency of the external DDR memory, On-Chip RAM and block RAM (BRAM) in the FPGA. Finally, we’ll round up with numbers on interrupt latency.
Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.
Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.
This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.
This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.
This article introduces the various memory hierarchy available when designing a MicroBlaze system using the Xilinx Vivado IP Integrator.
On chip ram or internal RAM, often abbreviated OCRAM or OCM has been around since the earliest System on Chips(SoCs). This articles goes over general purpose On-Chip RAM as well as more specialized forms such as Tightly Coupled Memory (TCM) and DMA buffers. We discuss major features and design considerations that could impact an embedded … Read more
This article will go over some aspects of the early bring-up experience using the BASEplatform™ on the Toradex Colibri iMX7 System on Module (SoM). It will also cover features and advantages of the Colibri SoM for embedded developers interested in using an RTOS or a bare-metal environment on the NXP i.MX7 SoC. The BASEplatform is … Read more
This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.