Embedded Software Insight
This article will go over some aspects of the early bring-up experience using the BASEplatform™ on the Toradex Colibri iMX7 System on Module (SoM). It will also cover features and advantages of the Colibri SoM for embedded developers interested in using an RTOS or a bare-metal environment on the NXP i.MX7 SoC. The BASEplatform is
This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.
In the last article about our recently launched BASEplatform product, we gave an overview of the various modules that can be part of the BASEplatform. In this article we go in a little more detail about an important aspect of any embedded software product, the API. In this case, the I/O API since it’s one
Two weeks ago, we launched our first embedded software product, BASEplatform. This article is the first of a series where we go into more details about the features and advantages of the BASEplatform. BASEplatform is designed to bring application developers all the necessary low-level components such as startup code, drivers, BSP, RTOS integration as well
We are proud to announce that we are jumping in the embedded software component market with the introduction of BASEplatform™. Tackling the fundamentals, BASEplatform is a collection of low-level interface modules, drivers, and board support packages. Designed from the ground up to provide the foundation of a successful embedded software design. Whether for a bare-metal project
In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a
Following up on the last piece about the NXP i.MX 7, this article looks at the ARM Cortex-M4 companion of the Cortex-A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare
One of our specialties at JBLopen is board bring-up, either for bare metal or various commercial and open source RTOSes. Despite the number of different platforms, CPU architectures and RTOSes out there, low level bring-up, BSP and driver development are rarely discussed in blogs and articles on the web. The same can be said about
Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 and 64 bits ARM processors such
In this article, I’ll explore the interrupt latency, also known as interrupt response time, of an ARM Cortex-A9 under various scenarios — and yes, it’s still on the Xilinx Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case
This article will go over some aspects of the early bring-up experience using the BASEplatform™ on the Toradex Colibri iMX7 System on Module (SoM). It will also cover features and advantages of the Colibri SoM for embedded developers interested in using an RTOS or a bare-metal environment on the NXP i.MX7 SoC. The BASEplatform is
This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.
In the last article about our recently launched BASEplatform product, we gave an overview of the various modules that can be part of the BASEplatform. In this article we go in a little more detail about an important aspect of any embedded software product, the API. In this case, the I/O API since it’s one
Two weeks ago, we launched our first embedded software product, BASEplatform. This article is the first of a series where we go into more details about the features and advantages of the BASEplatform. BASEplatform is designed to bring application developers all the necessary low-level components such as startup code, drivers, BSP, RTOS integration as well
We are proud to announce that we are jumping in the embedded software component market with the introduction of BASEplatform™. Tackling the fundamentals, BASEplatform is a collection of low-level interface modules, drivers, and board support packages. Designed from the ground up to provide the foundation of a successful embedded software design. Whether for a bare-metal project
In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a
Following up on the last piece about the NXP i.MX 7, this article looks at the ARM Cortex-M4 companion of the Cortex-A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare
One of our specialties at JBLopen is board bring-up, either for bare metal or various commercial and open source RTOSes. Despite the number of different platforms, CPU architectures and RTOSes out there, low level bring-up, BSP and driver development are rarely discussed in blogs and articles on the web. The same can be said about
Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 and 64 bits ARM processors such
In this article, I’ll explore the interrupt latency, also known as interrupt response time, of an ARM Cortex-A9 under various scenarios — and yes, it’s still on the Xilinx Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case