Articles by subject: interrupt

Histogram of interrupt latency distribution with pase fail sections for demonstration.

Estimating Worst Case Interrupt Latency at Runtime

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

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Interrupt latency distribution for a Cortex-A9 with cold cache.

Improving Interrupt Latency on the ARM Cortex-A9

Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 bits ARM processors such as the

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Histogram of access latency for random memory access on a Cortex-A9.

ARM Cortex-A Interrupt Latency

In this article, I’ll explore interrupt latency of a Cortex-A9 under various scenarios — and yes, it’s still on the Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case latency. Embedded Systems and Application Processors With the ever-increasing requirements

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Articles by subject: interrupt

Histogram of interrupt latency distribution with pase fail sections for demonstration.

Estimating Worst Case Interrupt Latency at Runtime

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

Read More »
Interrupt latency distribution for a Cortex-A9 with cold cache.

Improving Interrupt Latency on the ARM Cortex-A9

Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 bits ARM processors such as the

Read More »
Histogram of access latency for random memory access on a Cortex-A9.

ARM Cortex-A Interrupt Latency

In this article, I’ll explore interrupt latency of a Cortex-A9 under various scenarios — and yes, it’s still on the Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case latency. Embedded Systems and Application Processors With the ever-increasing requirements

Read More »