arm

i.MX7D M4 Bare-Metal Bring-up and Benchmark

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Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

Following up on the last piece about the NXP i.MX 7, this article looks at the ARM Cortex-M4 companion of the Cortex-A7 present in the i.MX 7. Or to put it another way, a Kinetis-on-chip since it’s very similar to a high-end Cortex-M4 based Kinetis. This article summarizes my experience writing a brand new bare … Read more

i.MX7D Sabre Bare-Metal Bring-up and Benchmark

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Close up shot of the NXP i.MX7 Sabre development board showing the SoC BGA chip.

One of our specialties at JBLopen is board bring-up, either for bare metal or various commercial and open source RTOSes. Despite the number of different platforms, CPU architectures and RTOSes out there, low level bring-up, BSP and driver development are rarely discussed in blogs and articles on the web. The same can be said about … Read more

Improving Interrupt Latency on the ARM Cortex-A9

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Interrupt latency distribution for a Cortex-A9 with cold cache.

Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9 which can help reduce interrupt latency. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 and 64 bits ARM processors such as the Cortex-A7. Newer cores have a simpler TLB, and most often than not an integrated L2 cache instead of the external L2 found on the A9. However, the Cortex-A9 is still a popular core, found on the Xilinx Zynq-7000 and NXP i.MX 6 SoCs to name a few.

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ARM Cortex-A Interrupt Latency

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Histogram of access latency for random memory access on a Cortex-A9.

In this article, I’ll explore the interrupt latency, also known as interrupt response time, of an ARM Cortex-A9 under various scenarios — and yes, it’s still on the Xilinx Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case … Read more