interrupt

Estimating Worst Case Interrupt Latency at Runtime

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Histogram of interrupt latency distribution with pase fail sections for demonstration.

This article shows a simple way of estimating worst case interrupt latency at runtime which can be implemented on most MCUs and RTOSes or even bare-metal. All that is needed is a hardware timer that can generate an interrupt after an arbitrary time delay. The technique is also rather non-intrusive, making it usable all the way to production without significantly affecting the application’s performance.

Improving Interrupt Latency on the ARM Cortex-A9

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Interrupt latency distribution for a Cortex-A9 with cold cache.

Continuing from the last post, this article explores features specific to early members of the ARM Cortex-A family such as the Cortex-A9 which can help reduce interrupt latency. Namely the L2 cache and TLB lockdown features found in those processors. It’s important to note that those two features are not available in more recent 32 and 64 bits ARM processors such as the Cortex-A7. Newer cores have a simpler TLB, and most often than not an integrated L2 cache instead of the external L2 found on the A9. However, the Cortex-A9 is still a popular core, found on the Xilinx Zynq-7000 and NXP i.MX 6 SoCs to name a few.

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ARM Cortex-A Interrupt Latency

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Histogram of access latency for random memory access on a Cortex-A9.

In this article, I’ll explore the interrupt latency, also known as interrupt response time, of an ARM Cortex-A9 under various scenarios — and yes, it’s still on the Xilinx Zynq-7000, since I still have that board on my desk from the last two articles. An upcoming follow-up article will describe methods of improving worst case … Read more